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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:17:40 12/02/2009 
-- Design Name: 
-- Module Name:    ALU_control - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ALU_control is
    Port ( funct : in  STD_LOGIC_VECTOR (5 downto 0);
           ctrl_out : out  STD_LOGIC_VECTOR (2 downto 0));
end ALU_control;

architecture Behavioral of ALU_control is

begin
	with funct select
		ctrl_out <= "000" when "100001", --21H
						"001" when "100100", --24H
						"010" when "100111", --27H
						"011" when "100101", --25H
						"100" when "100011", --23H
						"101" when "100110", --26H
						"111" when others;
					
	
end Behavioral;

library IEEE;
use IEEE.std_logic_1164.all;

package mips_alu_ctrl is
	component ALU_control
		Port ( funct : in  STD_LOGIC_VECTOR (5 downto 0);
				ctrl_out : out  STD_LOGIC_VECTOR (2 downto 0));
	end component;
end mips_alu_ctrl;